Christof Paar
Institution: Ruhr-Universität Bochum / CASA / Max Planck Institute for Security and Privacy
Research Hub(s):
Hub A: Future Cryptography
Hub B: Embedded Security
E-Mail: Christof.Paar@csp.mpg.de
Website: https://informatik.rub.de/paar/
Twitter: @ChristofPaar
Publications:
Stealing Maggie's Secrets – On the Challenges of IP Theft Through FPGA Reverse Engineering Analog Physical-Layer Relay Attacks with Application to Bluetooth and Phase-Based Ranging Reconfigurable Intelligent Surface for Physical Layer Key Generation: Constructive or Destructive? Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems Intelligent Reflecting Surface-Assisted Wireless Key Generation for Low-Entropy Environments LifeLine for FPGA Protection: Obfuscated Cryptography for Real-World Security How Not to Protect Your IP - An Industry-Wide Break of IEEE 1735 Implementations Explainability as a Requirement for Hardware: Introducing Explainable Hardware (XHW) HAWKEYE – Recovering Symmetric Cryptography From Hardware Circuits I see an IC: A Mixed-Methods Approach to Study Human Problem-Solving Processes in Hardware Reverse Engineering Towards Unsupervised SEM Image Segmentation for IC Layout Extraction Mirror Mirror on the Wall: Wireless Environment Reconfiguration Attacks Based on Fast Software-Controlled Surfaces IRShield: A Countermeasure Against Adversarial Physical-Layer Wireless Sensing Keys from the Sky: A First Exploration of Physical-Layer Security Using Satellite Links The Anatomy of Hardware Reverse Engineering: An Exploration of Human Factors during Problem Solving Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations A Cautionary Note on Protecting Xilinx' UltraScale(+) Bitstream Encryption and Authentication Engine On the Design and Misuse of Microcoded (Embedded) Processors — A Cautionary Note A survey of algorithmic methods in IC reverse engineering An Exploratory Study of Hardware Reverse Engineering — Technical and Cognitive Processes The Unpatchable Silicon: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations DANA Universal Dataflow Analysis for Gate-Level Netlist Reverse Engineering
