Amir Moradi

Amir Moradi

Institution: Ruhr-Universität Bochum / CASA

Research Hub(s):

Hub B: Eingebettete Sicherheit


Adresse: ID 2/605


Cryptanalysis of Efficient Masked Ciphers: Applications to Low Latency Composable Gadgets with Reused Fresh Masks: First-Order Probing-Secure Hardware Circuits with only 6 Fresh Masks Beware of Insufficient Redundancy: An Experimental Evaluation of Code-based FI Countermeasures Transitional Leakage in Theory and Practice - Unveiling Security Flaws in Masked Circuits Generic Hardware Private Circuits - Towards Automated Generation of Composable Secure Gadgets Automated Generation of Masked Hardware Low-Latency Hardware Private Circuits The SPEEDY Family of Block Ciphers - Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures FIVER – Robust Verification of Countermeasures against Fault Injections Inconsistency of Simulation and Practice in Delay-based Strong PUFs Countermeasures against Static Power Attacks – Comparing Exhaustive Logic Balancing and Other Protection Schemes in 28 nm CMOS Second-Order SCA Security with almost no Fresh Randomness Clock Glitch versus SIFA A Cautionary Note on Protecting Xilinx' UltraScale(+) Bitstream Encryption and Authentication Engine Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations Low-Latency and Low-Randomness Second-Order Masked Cubic Functions Second-Order Low-Randomness d + 1 Hardware Sharing of the AES SKINNY-AEAD and SKINNY-Hash When Real-World Snapshots Question Theory – Revisiting the t-Probing Security Model Impeccable Circuits Randomness Optimization for Gadget Compositions in Higher-Order Masking PROLEAD - A Probing-Based Hardware Leakage Detection Tool Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations A Comparison of x²-Test and Mutual Information as Distinguisher for Side-Channel Analysis Cryptographic Fault Diagnosis using VerFI Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version 3-Phase Adiabatic Logic and its Sound SCA Evaluation TI-PUF: Toward Side-Channel Resistant Physical Unclonable Functions Automated Probe Repositioning for On-Die EM Measurements The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs Impeccable Circuits II The Unpatchable Silicon: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs Glitch-Resistant Masking Revisited Exploring the Effect of Device Aging on Static Power Analysis Attacks Template attacks on nano-scale CMOS devices Low-Latency Keccak at any Arbitrary Order DL-LA: Deep Learning Leakage Assessment - A modern roadmap for SCA evaluations Let’s Take it Offline: Boosting Brute-Force Attacks on iPhone’s User Authentication through SCA New First-Order Secure AES Performance Records Re-Consolidating First-Order Masking Schemes Lightweight Ciphers on a 65 nm ASIC A Comparative Study on Energy Consumption Real-World Snapshots vs. Theory: Questioning the t-Probing Security Model SILVER – Statistical Independence and Leakage Verification Static Power Side-Channel Analysis – An Investigation of Measurement Factors