Countermeasures against Static Power Attacks – Comparing Exhaustive Logic Balancing and Other Protection Schemes in 28 nm CMOS2021
Research Hub B: Eingebettete Sicherheit
RC 6: Next-Generation Implementation Security
In recent years it has been demonstrated convincingly that the standbypower of a CMOS chip reveals information about the internally stored and processeddata. Thus, for adversaries who seek to extract secrets from cryptographic devices viaside-channel analysis, the static power has become an attractive quantity to obtain.Most works have focused on the destructive side of this subject by demonstratingattacks. In this work, we examine potential solutions to protect circuits from silentlyleaking sensitive information during idle times. We focus on countermeasures thatcan be implemented using any common digital standard cell library and do notconsider solutions that require full-custom or analog design flow. In particular, weevaluate and compare a set of five distinct standard-cell-based hiding countermeasures,including both, randomization and equalization techniques. We then combine thehiding countermeasures with state-of-the-art hardware masking in order to amplifythe noise level and achieve a high resistance against attacks. An important part ofour contribution is the proposal and evaluation of the first ever standard-cell-basedbalancing scheme which achieves perfect data-independence on paper, i.e., in absenceof intra-die process variations and aging effects. We call our new countermeasureExhaustive Logic Balancing (ELB). While this scheme, applied to a threshold im-plementation, provides the highest level of resistance in our experiments, it may notbe the most cost effective option due to the significant resource overhead associated.All evaluated countermeasures and combinations thereof are applied to a serializedhardware implementation of the PRESENT block cipher and realized as crypto-graphic co-processors on a 28 nm CMOS ASIC prototype. Our experimental resultsare obtained through real-silicon measurements of a fabricated die of the ASIC in atemperature-controlled environment using a source measure unit (SMU). We believethat our elaborate comparison serves as a useful guideline for hardware designers tofind a proper tradeoff between security and cost for almost any application.