Amir Moradi
Institution: Ruhr-Universität Bochum / CASA
Research Hub(s):
Hub B: Embedded Security
E-Mail: Amir.Moradi@rub.de
Adress: ID 2/605
Website: https://informatik.rub.de/impsec/
Publications:
Automated Generation of Masked Hardware Randomness Optimization for Gadget Compositions in Higher-Order Masking Impeccable Circuits Beware of Insufficient Redundancy: An Experimental Evaluation of Code-based FI Countermeasures When Real-World Snapshots Question Theory – Revisiting the t-Probing Security Model Clock Glitch versus SIFA SKINNY-AEAD and SKINNY-Hash Second-Order Low-Randomness d + 1 Hardware Sharing of the AES PROLEAD - A Probing-Based Hardware Leakage Detection Tool Cryptanalysis of Efficient Masked Ciphers: Applications to Low Latency Generic Hardware Private Circuits - Towards Automated Generation of Composable Secure Gadgets Transitional Leakage in Theory and Practice - Unveiling Security Flaws in Masked Circuits Composable Gadgets with Reused Fresh Masks: First-Order Probing-Secure Hardware Circuits with only 6 Fresh Masks Low-Latency Hardware Private Circuits Low-Latency and Low-Randomness Second-Order Masked Cubic Functions Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations A Cautionary Note on Protecting Xilinx' UltraScale(+) Bitstream Encryption and Authentication Engine Automated Generation of Fault-Resistant Circuits PoMMES: Prevention of Micro-architectural Leakages in Masked Embedded Software A Deep Analysis of two Glitch-Free Hardware Masking Schemes SESYM and LMDPL A Thorough Evaluation of RAMBAM Deep Learning Side-Channel Collision Attack PROLEAD_SW - Probing-Based Software Leakage Detection for ARM Binaries Exploring the Effect of Device Aging on Static Power Analysis Attacks Glitch-Resistant Masking Revisited The Unpatchable Silicon: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs Impeccable Circuits II The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations TI-PUF: Toward Side-Channel Resistant Physical Unclonable Functions 3-Phase Adiabatic Logic and its Sound SCA Evaluation Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version Cryptographic Fault Diagnosis using VerFI A Comparison of x²-Test and Mutual Information as Distinguisher for Side-Channel Analysis Automated Probe Repositioning for On-Die EM Measurements Static Power Side-Channel Analysis – An Investigation of Measurement Factors SILVER – Statistical Independence and Leakage Verification Real-World Snapshots vs. Theory: Questioning the t-Probing Security Model Lightweight Ciphers on a 65 nm ASIC A Comparative Study on Energy Consumption Template attacks on nano-scale CMOS devices Re-Consolidating First-Order Masking Schemes New First-Order Secure AES Performance Records Let’s Take it Offline: Boosting Brute-Force Attacks on iPhone's User Authentication through SCA DL-LA: Deep Learning Leakage Assessment - A modern roadmap for SCA evaluations Low-Latency Keccak at any Arbitrary Order Second-Order SCA Security with almost no Fresh Randomness Countermeasures against Static Power Attacks – Comparing Exhaustive Logic Balancing and Other Protection Schemes in 28 nm CMOS Inconsistency of Simulation and Practice in Delay-based Strong PUFs FIVER – Robust Verification of Countermeasures against Fault Injections The SPEEDY Family of Block Ciphers - Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures
