Tim Güneysu
Institution: Ruhr-Universität Bochum / CASA
Research Hub(s):
Hub A: Future Cryptography - CASA 1.0, 2019-2025
Hub B: Embedded Security - CASA 1.0, 2019-2025
Hub C: Secure Systems - CASA 1.0, 2019-2025
E-Mail: Tim.Gueneysu@rub.de
Adress: ID 2/609
Publications:
Gadget-based Masking of Streamlined NTRU Prime Decapsulation in Hardware Testing Security Equivalence in the Random Probing Model Short Paper: Mechanized Proofs of Masking Security INDIANA - Verifying (Random) Probing Security through Indistinguishability Analysis Correction Fault Attacks on Randomized CRYSTALS-Dilithium A Tale of Snakes and Horses: Amplifying Correlation Power Analysis on Quadratic Maps Quantitative Fault Injection Analysis Combined Private Circuits - Combined Security Refurbished SCARF: A Low-Latency Block Cipher for Secure Cache-Randomization LFSRs and Boolean Masking: An In-depth Security Analysis KeyVisor – A Lightweight ISA Extension for Protected Key Handles with CPU-enforced Usage Policies HAETAE: Shorter Lattice-Based Fiat-Shamir Signatures Combined Threshold Implementation Improved Circuit Synthesis with Multi-Value Bootstrapping for FHEW-like Schemes A New Perspective on Key Switching for BGV-like Schemes ABE Cubed: Advanced Benchmarking Extensions for ABE Squared pracy: A Practical Compiler for Attribute-Based Encryption in Python HADES: Automated Hardware Design Exploration for Cryptographic Primitives Implementing and Optimizing Matrix Triples with Homomorphic Encryption Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware Revisiting Fault Adversary Models - Hardware Faults in Theory and Practice Carry-Less to BIKE Faster BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster FIVER – Robust Verification of Countermeasures against Fault Injections Encoding Power Traces as Images for Efficient Side-Channel Analysis High-Speed Masking for Polynomial Comparisonin Lattice-based KEMs ClepsydraCache - Preventing Cache Attacks with Time-Based Evictions CINI MINIS: Domain Isolation for Fault and Combined Security VERICA-Verification of Combined Attacks: Automated formal verification of security against simultaneous information leakage and tampering A Holistic Approach Towards Side-Channel Secure Fixed-Weight Polynomial Sampling LifeLine for FPGA Protection: Obfuscated Cryptography for Real-World Security Challenges and Opportunities of Security-Aware EDA Proof-of-possession for KEM certificates using verifiable generation Risky Translations: Securing TLBs against Timing Side Channels Agile Acceleration of Stateful Hash-Based Signatures in Hardware Randomness Optimization for Gadget Compositions in Higher-Order Masking Write Me and I'll Tell You Secrets - Write-After-Write Effects On Intel CPUs
