Tim Güneysu

Tim Güneysu

Institution: Ruhr-Universität Bochum / CASA

Research Hub(s):

Hub A: Kryptographie der Zukunft
Hub B: Eingebettete Sicherheit
Hub C: Sichere Systeme

E-Mail: Tim.​Gueneysu@​rub.​de

Adresse: ID 2/609


Quantitative Fault Injection Analysis Challenges and Opportunities of Security-Aware EDA Proof-of-possession for KEM certificates using verifiable generation Risky Translations: Securing TLBs against Timing Side Channels Agile Acceleration of Stateful Hash-Based Signatures in Hardware Randomness Optimization for Gadget Compositions in Higher-Order Masking LifeLine for FPGA Protection: Obfuscated Cryptography for Real-World Security Combined Private Circuits - Combined Security Refurbished SCARF: A Low-Latency Block Cipher for Secure Cache-Randomization Implementing and Optimizing Matrix Triples with Homomorphic Encryption A Holistic Approach Towards Side-Channel Secure Fixed-Weight Polynomial Sampling Write Me and I'll Tell You Secrets - Write-After-Write Effects On Intel CPUs FIVER – Robust Verification of Countermeasures against Fault Injections Encoding Power Traces as Images for Efficient Side-Channel Analysis High-Speed Masking for Polynomial Comparisonin Lattice-based KEMs ClepsydraCache - Preventing Cache Attacks with Time-Based Evictions CINI MINIS: Domain Isolation for Fault and Combined Security BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster VERICA-Verification of Combined Attacks: Automated formal verification of security against simultaneous information leakage and tampering Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware Revisiting Fault Adversary Models - Hardware Faults in Theory and Practice Carry-Less to BIKE Faster