
Tim Güneysu
Institution: Ruhr-Universität Bochum / CASA
Research Hub(s):
Hub A: Kryptographie der Zukunft
Hub B: Eingebettete Sicherheit
Hub C: Sichere Systeme
E-Mail: Tim.Gueneysu@rub.de
Adresse: ID 2/609
Publikationen:
Revisiting Fault Adversary Models - Hardware Faults in Theory and Practice Proof-of-possession for KEM certificates using verifiable generation Risky Translations: Securing TLBs against Timing Side Channels Agile Acceleration of Stateful Hash-Based Signatures in Hardware Randomness Optimization for Gadget Compositions in Higher-Order Masking Write Me and I'll Tell You Secrets - Write-After-Write Effects On Intel CPUs VERICA-Verification of Combined Attacks: Automated formal verification of security against simultaneous information leakage and tampering Racing BIKE: Improved Polynomial Multiplication and Inversion in Hardware CINI MINIS: Domain Isolation for Fault and Combined Security Carry-Less to BIKE Faster BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster FIVER – Robust Verification of Countermeasures against Fault Injections Encoding Power Traces as Images for Efficient Side-Channel Analysis High-Speed Masking for Polynomial Comparisonin Lattice-based KEMs ClepsydraCache - Preventing Cache Attacks with Time-Based Evictions